In a data processing system with graphics capability, a system processor executing a graphics application program outputs signals representing matter to be displayed; this representation is generally abstract and concise in form. Such form is not suitable for the direct control of a display monitor; it is necessary to transform the relatively abstract representation into a representation which can be used to control the display. Such transformation is referred to as graphics rendering; in a system using a raster display monitor, the information comprising the transformed representation is referred to as a framebuffer.
The framebuffer representation must be frequently updated, by rewriting its contents in part or completely, either to reflect dynamic aspects of the display, or to provide for the display of images generated from a different application program. Each updating operation requires access to the memory in which a physical representation of the framebuffer is stored; generally a large number of locations in the framebuffer storage must be accessed for each updating operation. The speed of rendering the display is limited by the requirement for graphics memory access; the greater the number of bits in the graphics memory (framebuffer storage) that can be read or written in a given time period (the "memory bandwidth"), the better the graphics performance. Use of two-port video RAMs has permitted the update accesses to go forward independently of the refresh accesses, easing the update bandwidth requirement somewhat, but this aspect of the graphics operation remains a major problem in achieving real time dynamic displays.
Graphics memory bandwidth depends on the number of memory packages (chips) comprising the graphics memory, multiplied by the number of i/o pins per package; the product is the maximum possible number of bits that can be accessed in one memory transaction. Bandwidth is then a function of this maximum number and of the time required for a memory transaction.
From the point of view of obtaining large bandwidth, it is therefore desirable to use a relatively large number of i/o pins. However, recent developments in memory chip design have resulted in increasing numbers of bits per chip (referred to as "higher density"), while the number of i/o pins per chip has remained relatively constant. Higher density chips tend to be less expensive elements than lower density chips; further, designs using higher density chips can allocate less board space to memory chips than would be required by a design using lower density chips, a further element in achieving an economical overall design. Such high-density chips are therefore desirable design choices; but when such chips are used, there are fewer i/o pins per bit than there are when low density chips are used. This results in reduced memory i/o bandwidth, which degrades the graphics performance.
If, in order to obtain sufficient bandwidth, more chips are used than are in fact needed to store the framebuffer information, some of the memory is in effect wasted, which increases the cost of a system of such design.
It would therefore be desirable to provide a memory architecture which provides a large graphics memory bandwidth, while at the same time making efficient use of all the memory elements which comprise the memory.
If such increased memory bandwidth is to improve the graphics performance, it must be provided in a form which can be efficiently used. Many conventional graphics rendereing operations are carried out by a series of steps that are highly incremental in nature; that is, the value of a particular framebuffer pixel cannot be updated (and the framebuffer storage rewritten) until the updated value of an adjacent framebuffer pixel is known. Framebuffer updating carried out by means of such incremental operations requires frequent memory transactions, each involving a relatively small number of bits. The rendering performance of such a graphics system can be improved by decreasing the time required for a memory transaction, but will not be much improved by increasing the number of bits which can be addressed in a transaction.
It is therefore desirable to provide a graphics architecture which permits efficient use of the improved memory bandwidth.
It is an object of the present invention to provide a memory architecture for a data processing system with graphics capability which provides greatly increased graphics memory bandwidth, suitable for use in a highly parallel graphics rendering subsystem. It is a further object to provide such an architecture that is relatively economical to realize and is therefore suitable for use in low end systems. Additionally, it is an object to provide such an architecture that permits the entire memory capacity to be used by the system, by allocating the memory between graphics memory and system memory. It is yet another object to provide such an architecture that permits flexible (software configurable) allocation of the memory according to needs of a particular application and particular system configuration.